A power-rail electrostatic discharge (ESD) clamp circuit plays a critical role in achieving whole-chip ESD protection. A conventional ESD clamp circuit includes a clamp circuit and a detection circuit. The detection circuit detects whether an ESD event occurs on the power rails, and drives the clamp circuit to perform an ESD operation when the ESD event is detected.
As CMOS technologies approach a nanometer scale, for a transistor, a breakdown voltage of a gate oxide layer that is getting thinner and thinner also rapidly drops along with advancements in manufacturing techniques. Thus, a leakage current of the transistor device is correspondingly increased to significantly complicate ESD protection circuit designs. Therefore, there is a need for an ESD clamp circuit having a low leakage current for adapting to the ever-increasing CMOS technologies.